In a typical central processing unit (CPU), the instruction pointer is a binary counter (which is the origin of the term program counter) that may be one of many registers in the CPU hardware. The instruction cycle begins with a fetch, in which the CPU places the value of the instruction pointer on the address bus to send it to the memory. The memory responds by sending the contents of that memory location on the data bus. (This is the stored-program computer model, in which executable instructions are stored alongside ordinary data in memory, and handled identically by it). Following the fetch, the CPU proceeds to execution, taking some action based on the memory contents that it obtained. At some point in this cycle, the instruction pointer will be modified so that the next instruction executed is a different one (typically, incremented so that the next instruction is the one at the next sequential memory address).
Like other processor registers, the instruction pointer may be a bank of binary latches, each one representing one bit of the value of the instruction pointer. The number of bits (the width of the instruction pointer) relates to the processor architecture. For instance, a "32-bit" CPU may use 32 bits to be able to address 232 units of memory. If the instruction pointer is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or the CPU may compute some other value and load it into the instruction pointer by a pulse to its LOAD input.
To identify the current instruction, the instruction pointer may be combined with other registers that identify a segment or page. This approach permits a the instruction pointer with fewer bits by assuming that most memory units of interest are within the current vicinity.
When writing a multi-threaded program, the programmer may write each thread as a sequence of instructions without specifying the timing of any instruction relative to instructions in other threads.